Semiconductor substrates, particularly, silicon single crystal wafers (hereinafter, also simply referred to as “substrates”) are used as substrates for fabricating highly-integrated MOS devices. Many of the silicon single crystal wafers are substrates which are obtained by slicing a silicon single crystal ingot manufactured by the Czochralski (CZ) method.
In such a silicon single crystal wafer, oxygen introduced during single crystal production is present in a supersaturated concentration. The oxygen is precipitated in later device processing, and oxygen precipitates are formed in the substrate. When a sufficient amount of the oxygen precipitates are present in the substrate, the precipitates getter heavy metals, which are introduced during the device processing, in the substrate. The precipitates have an effect of maintaining clean the substrate surface, which is a device active layer.
A technique to which such effect is applied is called intrinsic gettering (IG) and used for preventing characteristics deterioration due to heavy metal contamination. Therefore, an appropriate degree of oxygen precipitation is expected to occur during device processing in a silicon single crystal substrate.
In order to promote gettering ability, oxygen precipitates of at least a predetermined density or concentration are desired to be present in the center in the thickness of a silicon single crystal wafer. As a result of past tests, it is believed that when 5×108 or more oxygen precipitates per cm3 are present midway between the surfaces of a silicon single crystal wafer, gettering ability for heavy metals, such as Fe, Ni, and Cu, is provided even in heat treatment in a low-temperature device processing wherein the highest temperature is equal to or less than 1100° C.
Meanwhile, silicon semiconductor substrates obtained by high-temperature heat treatment (hereinafter, referred to as “annealing”) of silicon single crystal wafers (hereinafter, referred to as “annealed wafers”) are widely used in fabrication of high-density highly integrated devices.
In the present disclosure, silicon single crystal wafers which have not undergone annealing before delivery are referred to as “mirror wafers,” and substrates before undergoing annealing are referred to as “substrates” so as to distinguish them from each other.
It is believed that the annealed wafers do not have grown-in defects such as COP (Crystal Originated Particles) on the substrate surfaces and have desirable device characteristics, for example, GOI(gate oxide integrity) characteristics. This is because such grown-in defects as are present near the substrate surfaces are diminished or eliminated through high-temperature annealing, and, as a result, defect-free layers are formed in the regions within several micrometers from the surfaces.
However, the annealed wafers are also believed to have inferior gettering characteristics compared with the previously-described mirror wafers without epitaxial deposition. A conceivable reason is that, generally, oxygen precipitation nuclei are eliminated by annealing of 1100° C. or more, and therefore oxygen precipitation does not occur in the device processing thereafter.
Manufacturing methods of annealed wafers using nitrogen-doped substrates as substrates have been proposed as examples of methods which compensate for insufficient oxygen precipitation in the annealed wafers (see Patent Documents 1 and 2 below).
This is because, when nitrogen dopant is added, thermally stable oxygen precipitation nuclei are formed during crystal growth, and they are not diminished or eliminated even during an annealing step; thus, oxygen precipitates are generated based on such oxygen precipitation nuclei in device heat treatment after annealing. When such substrates are used as substrates, oxygen precipitation after annealing can be promoted.
However, as the diameter of recent annealed wafers is increased from 200 mm to 300 mm, a new requirement of oxygen precipitation characteristics has emerged. The requirement is to control the oxygen precipitate density to be uniform in a substrate plane. The reason is that, if there is a location where the oxygen precipitate density is low in the substrate plane, gettering ability at that area is lessened, which leads to less device yield. In order to manufacture an annealed wafer in which the oxygen precipitate density is uniform in the substrate plane, growth conditions of nitrogen doped crystals have to be precisely controlled. In conventional techniques, the growth conditions of the nitrogen doped crystals are not taken into consideration. Therefore, annealed wafers manufactured by such techniques do not resolve this issue because locations where oxygen precipitation densities are low are generated in the substrate plane therein (see Patent Documents 3 and 4 below).
Also, manufacturing methods of annealed wafers may provide for oxygen precipitation densities that are uniform in the plane (Patent Documents 5 and 6 below). Japanese Laid-Open Patent Application (kokai) No. 2003-59932 (which is hereby incorporated herein for all purposes) discloses a method in which V/G, which is one of crystal pulling parameters, is adjusted to within a certain range so that the entire substrate becomes a special region called an OSF region. Also, Japanese Laid-Open Patent Application (kokai) No. 2003-243404 (which is hereby incorporated herein for all purposes) discloses a manufacturing method in which the crystal pulling parameter V/G is restricted to a range between about 0.175 and about 0.225. However, in such methods, since the crystal pulling parameter V/G is limited to an extremely narrow range, control of crystal pulling becomes difficult, which is a factor that lowers yield. In particular, an issue is that, since the uppermost limit of the crystal pulling speed is regulated, the pulling speed cannot be sufficiently increased, and productivity is lowered.
As described above, it has been difficult to manufacture an annealed wafer in which the oxygen precipitate density is high and oxygen precipitates are uniformly distributed in the substrate plane.
[Patent Document 1]
    Japanese Laid-Open Patent Application (kokai) No. 2000-26196 (which is hereby incorporated herein for all purposes)[Patent Document 2]    Japanese Laid-Open Patent Application (kokai) No. 10-98047 (which is hereby incorporated herein for all purposes)[Patent Document 3]    Japanese Laid-Open Patent Application (kokai) No. 2000-26196 (which is hereby incorporated herein for all purposes)[Patent Document 4]    Japanese Laid-Open Patent Application (kokai) No. 10-98047 (which is hereby incorporated herein for all purposes)[Patent Document 5]    Japanese Laid-Open Patent Application (kokai) No. 2003-59932[Patent Document 6]    Japanese Laid-Open Patent Application (kokai) No. 2003-243404